Intel XMP 3.0 Compatible DDR5 RAM: Kits Supported

One of the novelties that Intel has presented along with its new Alder Lake-S desktop processor architecture is the third generation of the so-called Extreme Memory Profile, which serves to increase the clock speed of the system RAM in order to obtain higher performance.

Due to the new generations of processors from Intel Core 12, they are compatible with DDR5 and this has a different operation from DDR4, especially due to the implementation of the PMIC in the modules of the new standard.

Which forces, as is customary for each memory standard, to renew not only the memory controller of the CPU, but also in the case of Intel to renew the mechanism for memory overclock. The result of this process in the Alder Lake-S architecture? XMP 3.0.

Intel Core 12 and DDR5 memory

In the Alder Lake-S architecture, Intel has added two different memory controllers, which are responsible for communication between the CPU and RAM, which must be done taking into account specific times so that it is fluid and not there are errors of any kind.

The first of these memory controllers is recycled from Rocket Lake-S and is the one that communicates with the DDR4 memory, but in the case of the second controller, the one that is in charge of communicating with the DDR5 memory, the only official information we have is that memory modules supported by DDR5-4800, so any higher speed DDR5 module is considered by the processor operating in Gear 2 mode.

XMP 3.0 on Intel Core 12

One of the novelties in the Alder Lake-S architecture is the third generation of the Extreme Memory Profile or XMP 3.0, which is its most important update since 2007, but we better go to the new features that it incorporates.

The current specification indicates that each memory module must have two operating profiles specified by the manufacturer, which in XMP 3.0 will increase to three. A memory profile is nothing more than telling you at what speed and voltage to operate. In addition, it allows us to store two personalized profiles that we can reconfigure at any time that is necessary.

These changes are influenced by the integration of the PMIC, an integrated circuit within each DDR5 module that is responsible for regulating the voltage at which the module operates. Since the Extreme Memory Profiles are based on varying the voltage in the face of memory overclocking, this has forced Intel to create an XMP 3.0 profile for DDR5.

The Gears in the Intel Core 11 and 12

Intel introduced the Gears in the Rocket Lake-S memory controller, the architecture of the 11th generation of its Intel Core CPUs. In this processor, the maximum supported DDR4 memory was the DDR4-3200 modules, so in the face of much faster memories and to avoid operating problems they introduced the Gear 2 mode, which consists of lowering the clock speed of the controller. memory in half. The consequences? The power to support faster memories, but in exchange for cutting the bandwidth between the processor and the RAM.

With regard to DDR5 Intel has added the same mechanism, but the memory controller supports memories up to DDR5-4800. So to make use of faster memories the Intel Core 12 has to be put in Gear 2 mode, where a new operating mode has been added, called Gear 4, which makes the memory controller work at 1/4 of the MCLK instead of half as in Gear 2 mode.

BCLK, QCLK and MCLK with XMP 3.0 and DDR5

The MCLK is the clock speed of the RAM memory, which in the case of DDR5 from the moment it is Dual Data Rate memory is half its transfer speed. Instead, the BCLK is the base clock rate at which the integrated memory controller communicates, and the QCLK is the multiplier.

The problem we have in the case of DDR5? We do not know at the moment what are the supported BCLK and QCLK speeds for DDR5 and what modes each memory module supports. It should be noted that the XMP 3.0 profiles are based on a combination of both elements to deduce both the MCLK and the transfer speed with RAM.

In the design of processors it is normal to reuse parts of the same processor, since we will not be able to place DDR4 and DDR5 memories at the same time, we can deduce that some elements such as the clock speeds of the IMC are maintained, but we do not know which ones correspond to each Gear.

DDR5 memory modules with XMP 3.0 support

Intel has published a comprehensive list of DDR5 memory modules that have been certified to support XMP 3.0 and among them we find some modules that are faster than DDR5-4800, which shouldn’t surprise us from the moment it inherits the form of access the RAM of its predecessor (the Gear modes) and apply it to the DDR5.

The list of modules that you see in the table belongs to the Qualified Vendor List or Qualified Vendor List that according to Intel comply with the XMP 3.0 standard. All of them are 32 GB kits made up of two 16 GB modules. In any case, despite the fact that the data from Intel are really austere in terms of the operation of the Gear modes in the Intel Core 12 as well as the XMP 3.0 in the face of overclocking, we must bear in mind that both are closely related , since depending on the clock speed of the RAM our Intel Core 12 will work in one mode and another.

One information from the table that we highlight is the fact that the CAS latency or the highest supported access times are 40-40-40-80. This means that very high DDR5 bandwidths with higher latency might not be supported for overclocking via XMP 3.0 on Intel Core 12.

Keep in mind that the transfer speed is not related to latency, in the table itself you can see how there are differences in latencies for the same transfer speed. Our conclusion is that any module with latencies greater than 40-40-80 will not be compatible with XMP 3.0.