Updated 20 October 2026.
A CCD is a physical core-containing die used in many AMD chiplet processors. A CCX is a core complex: a group of CPU cores organized around shared resources such as L3 cache. One describes a piece of silicon; the other describes how cores are grouped.
Start with the parts
| Term | Meaning | Important limit |
|---|---|---|
| CPU core | A processing core that runs instructions. | Core count is different from thread count. |
| CCX | A core complex sharing relevant resources. | Its core and cache layout changes by architecture. |
| CCD | A core-containing chiplet die. | It does not have one universal CCX or core count. |
| I/O die | A separate die handling memory and other connectivity in applicable chiplet designs. | Not every Ryzen product uses this same arrangement. |
Why older explanations mention four-core CCXs
Common Zen 2 desktop chiplet designs used two four-core complexes within a CCD, with enabled cores varying by processor. AMD’s EPYC 7002 tuning guide documents the same two-CCX structure in that server generation. That layout explains older discussions about crossing CCX boundaries, but it is not a permanent definition of CCX.
With Zen 3, AMD moved to an eight-core complex with a larger shared L3 arrangement in relevant designs. AMD’s Zen architecture overview describes this evolution. The core complex did not disappear; its organization changed.
A concrete Zen 3 example
AMD’s EPYC 7003 microarchitecture overview describes one CCX per CCD, with up to eight cores and shared L3 cache. This is a documented example, not a specification for every desktop, laptop and server processor AMD sells.
Later families also need their own documentation. Dense server cores, mainstream desktop cores, mobile designs and 3D V-Cache products can have different layouts. A Ryzen series number alone is not enough to infer every physical detail.
What the layout changes in practice
Cores sharing a local cache can exchange some data differently from cores that communicate across chiplets. That can affect latency and scheduling, but it does not create a universal rule that more CCDs are bad or that every game must be pinned to one complex.
Our Infinity Fabric clock guide explains the separate clock terminology. FCLK is not another name for a CCD or a CPU core’s boost frequency.
Read specifications for the exact processor
- Identify the architecture and exact model.
- Check enabled cores and threads.
- Separate L2 and L3 cache from a combined total.
- Look for model-specific chiplet and stacked-cache details.
- Use workload evidence before changing scheduling or memory settings.
AMD’s processor specification tables are a starting point. Manufacturing yield or disabled-core claims require their own evidence; the existence of chiplets does not prove how every competing processor is tested or sold.
FAQs
Is a CCD the same thing as a CCX?
No. A CCD is a physical die; a CCX is a group of cores and shared resources.
Did CCX disappear with Zen 3?
No. Relevant designs changed to a larger core complex rather than removing the concept.
Does every Ryzen have separate CCD and I/O dies?
No. Product families and generations differ, including monolithic and other layouts.
Does more L3 cache mean every core can access it equally?
Not necessarily. Cache location and sharing boundaries matter alongside the total capacity.