Virtual Memory in a CPU, Implementation and Operation in x86

Every CPU, regardless of its architecture, generally has two types of pins to communicate with the system’s RAM memory.

• Data Pins from where data is transmitted to and from memory.
• Addressing Pins where the memory is indicated where the data is.

But what does the addressing indicate? The RAM memory is physically organized in a table and when we access a specific data directly, what we do is mark in which row and column it is located, if for example our addressing is 6 bits then the memory may have 64 elements (2 ⁶ ) of which about 3 bits will tell me the row and another 3 bits will tell me the column where the data is located.

Utility and Definition of Virtual Memory

Virtual addressing does not work by pointing to memory addresses directly, but instead uses virtual addresses, which are organized by memory pages.

The first 8 and 16-bit CPUs that appeared on the domestic market only supported physical addressing, it was not a problem at that time because those systems only ran one application at the same time, but over time and as more powerful personal computers came out. it became necessary to integrate more sophisticated ways to handle access to RAM memory provided that environments with several applications running at the same time did not have problems when working and therefore one application did not access the memory space of another and even the operating system.

That is why the PC, starting with 80286, Intel began to include an MMU in its CPUs that addressed memory by segments, but it was hardly used and it was not until the arrival of 80386 that the MMU improved to support segments and pages for the direction that the PC Operating Systems gave an important advance in terms of quality.

As a historical note, when Microsoft released Windows 3.1 in the early 90’s, it only made it work with a 386 system onwards by making a memory paging MMU essential for use. From 80386 onwards, all x86 systems, including 64-bit ones, use logical addressing that is converted into physical addressing by the MMU so that the controller integrated in the RAM itself can understand what data to search for.

Not only RAM lives the CPU

The CPU to communicate with any memory device uses virtual addressing, the MMU is in charge not only of managing the communication of the CPU with the RAM, for the communication of the CPU with other I / O peripherals such as solid disks and solid disks connected to different interfaces the MMU communicates with the IOMMU.

Pages, tables and directories

The standard as of 80386 was that each page is 4KB in size (22 bits of the address).

From Pentium Pro (P6) onwards, Intel added to its CPUs the ability to handle pages of 4 MB in size, but it must be taken into account that both the Windows NT kernel and the Linux kernel were created when this option It was not available in x86, so the standard size of the pages of those operating systems and most of them is 4 KB, since their first versions are Pre-Pentium Pro and for backwards compatibility with applications this has not changed and their file systems are still based on 4KB pages which is what we are going to use to understand how it works.

To better understand the organization of the hierarchy, imagine the memory page as a written document.

These documents / pages are stored in the so-called Page Table, think of it as a folder where documents are stored and organized.

But there is one more level and the Page Table / Document Folder is stored in the Page Directory which is like a file cabinet that we call Page Directory.

The operating system and applications refer to memory addresses in a virtual way, the memory address begins first with the bits that indicate the Page Directory, then the Page Table, and then where the data is located within the page.

Virtual memory on contemporary x86 CPUs

All x86 CPUs that are currently on the market are 64 bits, they are also known as x86-64 or x64, regardless of whether they are Intel or AMD, they all work in the same way.

However, although its addressing is 64 bits, it really only addresses up to about 48 bits, this is because the first 16 bits are special bits that indicate how the MMU should treat the memory page, the table or the directory.

1. NX (No eXecute) : The NX bit when active indicates that there is no executable code in that page, table or directory of virtual memory and therefore it will not interpret certain bits as instructions for the CPU but only as data.
2. First bit reserved for the operating system.
3. Second bit reserved for the operating system.
4. Third bit reserved for the operating system.
5. G (iGnored): Tells the CPU to ignore that memory page, table or directory and go to the next one.
6. S (Size): Marks the size of the memory page (4KB or 4MB).
7. The value of this bit is always 0.
8. A (Available): Marks if the data is being accessed by a process at that moment, this bit is managed by the operating system.
9. D (Dirty): It is used to mark that the memory page does not have to be copied to the CPU cache.
10. The value of the next bit is always 0.
11. W (Write): marks if the page can be modified (write).
12. U (User): Check if the memory page is accessible by the Operating System (Supervisor) or by the applications (User).
13. R (Read): Check if the memory page can be read. Check whether or not the data on this page can be read.
14. P (Present): This bit is marked when the operating system moves the memory page to a lower level in the memory hierarchy, for example, that it is copied to the hard disk or a solid disk.

These bits allow the MMU to control the access of the different applications and the operating system to the system memory, it must be taken into account that the MMU only acts under the orders of the operating system of the system and it is this that has the maximum authority when it comes to virtual memory management.

Virtual memory and non-x86 architectures

Architectures based on other sets of registers and instructions such as ARM, PowerPC, MIPS, RISC-V also have support for virtual memory but under their own standards. For simplicity, in this report, we have decided to give as an example the operation of the CPUs with the ISA x86-64.