Reasons Why 3D NAND Memory Doesn’t Go Below 40nm

The lithography on the chips used in processors as we know them has long been in a struggle to reduce its manufacturing processes, and we are seeing the nanometers get smaller and smaller. However, when it comes to 3D NAND memory , it has been “stuck” at 40nm for quite some time now, and the trend is for it to remain that way at least in the medium term. Why don’t they improve the lithography of memory? We will tell you everything below.

3D NAND technology was first introduced in 2013, and Samsung did a great job of improving it in 2015; However, since then neither Samsung nor its competitors have made further improvements to this memory beyond creating more and more layers to increase density. So if the 3D NAND memory is 40nm, why don’t we see improvements with smaller nodes like 32nm, 20nm, etc.?

Why 3D NAND Memory Doesn't Go Below 40nm

The answer is that it is almost impossible to reduce lithography because of how, specifically, the communication channels between layers are manufactured and we will explain it to you below.

This is how 3D NAND channels are manufactured at 40 nm

To explain why the lithography of 3D NAND memory cannot be reduced much more we will use Toshiba’s BiCS structure (now used by KIOXIA) as an example.


  1. First, very narrow holes are made in all layers of the 3D NAND. Today these holes have an aspect ratio of about 60: 1, which is quite remarkable. Consider that for this lithograph, a one-inch (2.5 ″) diameter hole would be 1.5 meters long. These holes are like this, with walls almost perfectly parallel from top to bottom that go through all the layers of material and that serve to communicate all with each other.
  2. These holes are then filled with great precision with 5 layers of material:
    1. The initial layer is silicon oxide (SiO2), which makes the hole even narrower. This is shown in pale blue in the diagram that we are going to put below.
    2. Then it is covered with another thin layer of silicon nitride (Si3N4) also from top to bottom, making the hole even narrower. This is the charge capture layer and is shown in yellow.
    3. There is a very thin third layer of SiO2, which makes the hole even narrower.
    4. The next layer is conductive polysilicon. This layer is shown in red and serves as the data transmission channel.
    5. Finally, the little space that remains is filled with SiO2 (blue) again. This final insulating filler helps to “thin” the canal so that it performs better and is more stable.

Relleno agujeros 3D NAND 40 nm

Thus, the thickness of the layers that fill the holes determine their minimum diameter, and although we have shown it here as “large” in reality, the thickness of each inner layer is only a few atoms thick and it is practically impossible to make them smaller. .

For this reason 3D NAND memory will have to remain at 40 nm for the foreseeable future, and that is why all the efforts of manufacturers in recent times is to increase the number of layers that pass through these communication holes, the logic within the matrix and improved stair setups, but not in reducing lithography because at this point it is physically almost impossible.