So far we have seen the many ways that SSD controllers have to maximize device life, always trying to reduce write and erase cycles, which are the ones that cause wear. Today we are going to discuss how the internal NAND of SSDs is managed for the same purpose, prolonging their useful life in order to maximize their life expectancy.
In addition to performance, one of the biggest goals for SSD designers is that they are durable, and they use a combination of various techniques to do this. In some models, and it is what we are going to see today, the SSD controller is even capable of managing the internal workings of the NAND Flash memory chips themselves . Let’s see how they do it.
Not all controllers can manage NAND
Although this seems like a very important task (that the controller manages how the memory chips work, it seems obvious, right?), In reality not many controllers adopt this approach, and in fact this is a technique that generally is not available, although more and more controller manufacturers are implementing it.
Why is it like this? For intellectual property issues. Basically, the makers of the controllers are not the same as the NAND Flash memory chips, and therefore some do not want to share their designs with each other, since in order for the controller to manage the internal NAND, it must know exactly how it works and have control over it.
This means that in order for the SSD controller to manage the internal NAND, said controller will be dedicated to a single brand of NAND, that is, it would be a controller specifically designed for a single NAND model or even for a single family of SSDs. You will understand that, therefore, there are very few cases that we will find, and most are with closed deals or from manufacturers that manufacture their own NAND and controller, without resorting to third parties.
This is how the internal NAND is managed from the controller
Suppose we have an SSD manufacturer with a NAND provider who is willing to disclose the design information for their chips. In that case the SSD controller could manage many variables that can be controlled by changing the internal configuration of the internal NAND Flash chips, and if what we want is to maximize the life of an SSD, then the parameters that influence the errors are modified bit:
- Thresholds between levels in MLC.
- Programming times and algorithms.
- Physical placement relationships between adjacent cells.
- Methods for releasing electrons that get trapped along the way.
There are a few more methods that can help maximize the life of the SSD and that can be managed by the controller, but they are so highly internal that they really have no impact or interest to the user.
To give you an idea of how this works let’s look at just one parameter, MLC level detection. When an MLC flash memory is programmed, two bits are placed in a single cell and it has one of these four levels:
- Unloaded.
- 1/3 load.
- 2/3 load.
- Fully charged.
Certain, inevitable problems can cause these levels to deviate from their benchmark. Electrons can get trapped in the rust of communication tunnels, and this can make the floating gate appear to have a higher charge than the programming algorithm actually placed on it. Thermal influences and other reasons can drain electrons from the cell, reducing its charge, or readings and writes from adjacent cells can add or remove electrons from the floating gate.
A controller that understands these phenomena can adjust the detection thresholds within the NAND chip itself to help reduce the chance of a bit being misinterpreted. If a cell is assumed to be 2/3 full, but it appears to be 1/3 full, will it read as 1/3 or 2/3? If the SSD controller manages these thresholds to compensate for other factors, the impact this source of bit errors would have can be reduced.
Clearly, this is a pretty extreme way to squeeze every last bit of SSD lifespan, but you know that every grain of sand counts and the sum of all makes the lifespan of SSDs ever longer.
