AMD has surprised locals and strangers, Intel included with its new vertical stacking technology for its processors, where as we know this technology comes from TSMC. The novelty is that it will hit the market earlier than expected and in current Zen 3-based CPUs, so the provision of the new microarchitecture will arrive soon and well before Zen 4. What is AMD’s 3D Chiplet technology called 3D? V-Cache Stack and what does it consist of?
It has been at Computex 2021 where AMD has surprised everyone with the new announcement in its range of gaming CPUs for the end of 2021 to compete against Intel’s Alder Lake-S. The novelty is only one, but it will skyrocket the performance of the processors and has given us another clue about the design of Zen 3. This will be 3D V-Cache Stack with TSMC at the helm.
AMD 3D V-Cache Stack, TSMC’s X3D implementation for Zen 3
The company already advised in 2018 that it was working on a new layered development model in the purest Intel Foveros style called X3D, and since then we have only seen brush strokes. At least until AMD has pulled the canvas and shown nothing less than a prototype Ryzen 9 5900X with vertical stacking technology for SRAM as an L3 cache.
The data is partly concrete, but also partly concise and we will surely talk more about this technology in the future. But the novelty is the novelty and the data is starting to come out and it’s really interesting. On the one hand, AMD confirms that this 3D V-Cache Stack technology will reach current CPUs with Zen 3 architecture, but to be more specific, it will reach Ryzen CPUs exclusively, at least for now and waiting for Zen 4.
This excludes the new Milan server processors and the Threadripper, so AMD seeks to stand out in the sector where there is more competition today: in gaming or maistream.
The CPUs are not yet in production, but are expected to come shortly with TSMC to be released at the earliest in late 2021 or early 2022, curiously around the Alder Lake-S presentation and launch dates. At the same time this shows that AMD will take at least 6 more months to launch Zen 4 as such.
On the other hand, it is curious how these statements do not affirm or deny whether we will see them only on the desktop or this technology will also be extended to laptops with monolithic die, and by default, it is not specified whether they will reach the new APUs.
The Physical Limits of 3D V-Cache Technology Revealed
But we go further, since AMD specifies 1 3D V-cache stack for each chiplet, that is, in the Ryzen 9 we have a total L3 amount of 192 MB . Most surprising of all, AMD itself claims that V-Cache stacks can go up to 8 stacks, also called 8-hi.
Logically, in the future we would be talking about no less than 512 MB of L3 plus the cache that the CCDs have, a real outrage that can boost the performance of any processor to limits that right now we can’t even imagine.
The current problem and for which no more stacks are implemented is the height. AMD has had to reduce the overall height of the CCD and SRAM to maintain the heights that the original Ryzen had for the IO die.
Die size, heat and unknowns
It is not the first design as such in 3D that we see, but it is the first that is shown in a CPU that is currently on the market as an evolution of it. The doubts are being generated and as such, the speculations continue their course. But in the meantime we have confirmation of the size of the AMD 3D package: 6 x 6 mm , that is, an area of 36 mm2 is what the 3D V-Cache technology will occupy in the new Ryzen.
As the SRAM is on top of the CCDs, AMD has had to add two silicon brackets to the sides of it, welded to the dies, which equalizes the height of the assembly and also allows the heat output of the cores to be optimal and it hardly has a negative effect.
This is possible because unlike the added Cache, the two spring silicons do not include TSV, while logically the first does. This hybrid approach according to AMD itself allows the density of the interconnects to be increased 200 times and the overall efficiency of the interconnects is improved up to 3 times, so we can imagine the number of pipes that have been created for that purpose.
The improvements are very representative as seen in the demonstration of the Ryzen 5900X with 3D V-Cache: + 12% in Gears V, an average increase of 15% in gaming and a performance of up to 2 TB / s of total internal bandwidth on the processor and its cache, which means that for the first time in history the L3 would outperform the L1.
It remains to be seen if, indeed, AMD will introduce these 64 MB of L3 in all models or will only include 32 MB in those that carry a single CCD, where at the same time the question arises as to whether these new processors already baptized as Zen 3+ will arrive at a higher price.
If indeed this 3D V-Cache manages to improve gaming performance by 15% on average, can Intel counteract this effect with Alder Lake-S when it is a totally new architecture and it seems that it is not focused on the gamer as such?
For now we know that from the outset we will have these Ryzen, and that the next processors to include 3D V-Cache will be the new Milan-X, which should arrive in 2022 to further boost its performance.
