After the official presentation of the NVIDIA H100 with all its extremely amazing news, Intel now arrives and hits the table with a preview of the nearest future and a preview of what is to come in the world of AI and HPC. Rialto Bridge will be the defining and final point of GPUs as we know them today, as the future lies with XPU under Falcon Shores. Meanwhile, these new GPUs are a giant step for Pat Gelsinger to carve out a significant niche in the key industry that dominates the world today.
What is presented by the company, without performance in between, represents the next evolutionary step compared to Ponte Vecchio, GPUs that have not yet reached the market as such and instead already have successors. What is revealed focuses on 6 key aspects that we are going to break down, although the statements are brief as expected.
Intel Rialto Bridge, the most beast GPU designed so far
There are no big news here and some of them are to be expected, we could perfectly say that Rialto Bridge is a logical evolution of Ponte Vecchio following a very similar structure and we would be right. The first thing we have to take into account is that Intel’s IDM 2.0 strategy, which has the Ponte Vecchio GPU as its bastion, will reach a much more advanced level and that its main attraction will be the node changes in its different parts.
They haven’t been specified as such, but there are some rumors that Link Tiles could go to 5nm under TSMC, GPU dies on N4 and caches and other parts like Passive Die Stiffeners with Intel 4.
But, on the other hand, the slides shown eliminate one of the factors discussed a moment ago, since they curiously do not show Intel’s RAMBO Cache. This could indicate that Intel is going to include it within the GPU Tiles and thereby create more complex chips that could arrive with its Intel 4 manufacturing node and thus leave TSMC aside in this part of the game.
The fact of using HBM3 memory is also rumored , which would give a higher bandwidth and forces Intel to update its Xe Link architecture . It must be understood that any accelerating GPU of this type has memory bandwidth as its main limitation, performance is proportional to it, so that is why Intel announces more FLOPS and GT/s without giving further explanation.
That said, let’s jump to other equally important tasks with Rialto Bridge.
OAM 2.0, the consumption and increase of Cores
The type of socket that Intel will use for Rialto Brigde will be OAM 2.0 , which is a surprise since we did not know anything about it and also, according to what has been said, it will suppose a brutal figure in terms of capacities and consumption, since we have passed 700 watts with its first version at no less than 800 watts in this second one.
This increase is really intended to achieve more efficiency, since if we take into account that Ponte Vecchio includes 128 EUs, Rialto Brigde goes up to 160 Cores Xe under its belt, an increase of 25%, which given the increase of 100 watts It actually results in greater efficiency.
As for performance itself, Intel assures that we will see it take off by 30% , which is not impressive given the figures we have presented for Cores, but it is a leap forward in general terms in the absence of seeing the final frequencies.
Finally, and before talking about the future as such of this technology, Intel has set the date of Sampling 2023 for Rialto Bridge without specifying any quarter, figures very similar to those of NVIDIA with H100 and its Grace servers, where here those of Huang they have some advantage. And it is that the objective of Intel is clear if we look at the roadmap that it has provided: 2023 will be the year where the new Xeon and Rialto Bridge will arrive and in 2024 or 2025 make the leap to Falcon Shores , the architecture that will unite both in a new concept called XPU .
The future is Falcon Shores, the XPUs that will revolutionize the market
Falcon Shores will be the implementation with Tiles in a flexible and scalable way, a twist to what we have seen with the NVIDIA Grace SUPERCHIP where with EMIB and Foveros 3D Intel makes the leap to a single modular product that through a single socket can have all kinds of products to suit the consumer. From GPUs, CPUs to a mixture of both, this XPU concept will clearly be the dominant one in the industry to the point that we do not rule out the possibility of including some parts of an FPGA.
Intel gives more or less interesting details, since it states that with Falcon Shores the performance per watt will be increased by up to 5 times, the density per x86 socket by 5 times and the memory capacity and B/W in the same value, a concept which will later be imported to PC in a much simpler and above all cheaper way where luckily we will not have as many changes as such (lower price).
And it is that we start from a very decent CPU and GPU base that will only be enhanced by modular packaging and interconnection technologies, moving Intel directly to MCM architecture as AMD is going to do with Zen 4 and its iGPUs.
